1. Field of the Invention
Embodiments of the present invention relates to a delay locked loop (DLL), and more particularly, to a DLL that includes a duty cycle corrector to correct a duty cycle of a DLL output signal and controls one delay circuit to be commonly used in a duty cycle correction operation and a locking operation of the DLL.
2. Description of the Related Art
In semiconductor circuit technology, a clock signal is used as a reference signal for adjusting operational timing in a system or circuit. When an external clock signal is inputted to a circuit or system, a clock skew inevitably occurs. Such a clock skew is typically corrected to generate an internal clock signal having the same phase as the external clock signal. To correct the clock skew, circuit technology such as a DLL or a phase locked loop (PLL) is used.
The DLL is less influenced by noise than the PLL. Therefore, the DLL is widely used in a synchronous semiconductor memory device such as a DDR SDRAM (Double Data Rate Synchronous DRAM).
Meanwhile, as semiconductor technology develops, the size of elements has been reduced, and an operating speed of the elements has gradually increased in proportion to the size reduction. The increase of the operating speed may distort a clock signal inputted to a circuit or system. Thus, a duty cycle of the clock signal may frequently deviate from 50%. The deviation may cause malfunction in the circuit or system such as a DDR system that operates based on rising and falling edges of the clock signal. Typically, such a problem is overcome by adding a duty cycle corrector (DCC) as illustrated in FIG. 1. As known to those skilled in the art, a duty cycle D is defined as the ratio between the pulse duration (t) and the period (T) in the case of a rectangular waveform (D=t/T), so that the pulse is active in the pulse duration (t).
However, the addition of the DCC may cause other problems. Although it is not illustrated in FIG. 1, the DCC 20 includes a delay circuit. In this case, the delay circuit and a replica delay circuit 17 included in a DLL 10 may increase the power consumption and chip area of the circuit or system. In addition, if an input clock signal RefCLK has a high frequency and a duty cycle of the input clock signal RefCLK deviates from approximately 50%, the input clock signal RefCLK may disappear while passing through a plurality of delay circuits in the DLL 10 and the DCC 20 as illustrated in FIG. 2 because the duty cycle D has decreased to approximately 0%. This may occur because NMOS and PMOS transistors in a CMOS logic circuit forming the delay circuit have different driving strengths from each other. As a result, a maximum operating frequency of the input clock signal RefCLK inputted to the DLL may be limited by this phenomenon.